1. Field of the Invention
The present invention relates to: a display control substrate, such as a thin film transistor (thin film transistor) substrate, in which a TFT or the like is provided as a transistor element, for each of a multiplicity of pixel sections provided in two dimensions, used in an active matrix-type liquid crystal display device and the like, for example; a method for manufacturing the display control substrate; a liquid crystal display panel using the display control substrate; and an electronic information device using the display control substrate in the liquid crystal display panel, such as a television device, a monitoring device, a personal computer (e.g., laptop personal computer), an amusement electronic device and a game device.
2. Description of the Related Art
Conventionally, in the active matrix-type liquid crystal display device, the TFT is used as a switching element for each of a plurality of pixel sections provided in a matrix in a display section and as a semiconductor element making up a drive circuit section provided at the periphery of the display section.
Wirings of the TFT includes a gate electrode wiring, a source electrode wiring, a drain electrode wiring and the like. In a conventional method for manufacturing a TFT substrate, the gate electrode wiring and the source electrode wiring are formed in separate mask steps since the gate electrode wiring and the source electrode wiring intersect each other, and thus two layers of masks are required. As a result, in order to complete the TFT, for example, in the case of an inversely staggered TFT, five layers of masks are required in order to form a gate electrode wiring, a semiconductor island, source/drain electrode wirings, a contact hole in an interlayer insulation film and a transparent electrode. This is a cause of increasing the lead time, reducing the yield, increasing the manufacturing cost and the like.
FIG. 8 is a top view showing an exemplary essential structure of a TFT substrate used as a switching element for a pixel section of a conventional active matrix-type liquid crystal display device. Herein, an inversely staggered TFT will be described as an example.
In FIG. 8, on a TFT substrate 20, gate electrode wirings 21 and compensation capacitance (Cs) wirings 22 are repeatedly provided in parallel to each other. A semiconductor island 23a is provided on the gate electrode wiring 21 via a gate insulation film (not shown). The semiconductor island 23a is made of an intrinsic semiconductor layer, which becomes a channel region of the TFT, and an impurity-doped semiconductor layer (e.g., n+ semiconductor layer). On the compensation capacitance wiring 22, a semiconductor island 23b which becomes a part of a compensation capacitance upper electrode is provided via a compensation capacitance insulation film (not shown). The gate insulation film and the compensation capacitance insulation film are made of the same insulation film material and they are provided so as to cover the substrate. On top thereof, a source electrode wiring 24 is provided via the insulation films so as to intersect the gate electrode wiring 21 and the compensation capacitance wiring 22.
The source electrode wiring 24 is formed so as to have a portion extending over to the semiconductor island 23a. An extension portion 24a of the source electrode wiring 24 is electrically connected to the semiconductor island 23a. In addition, a drain electrode wiring 24b is provided so as to extend from the semiconductor island 23a to a semiconductor island 23b. The drain electrode wiring 24b is electrically connected to the semiconductor island 23a and the semiconductor island (a part of the compensation capacitance upper electrode) 23b. A transparent electrode 25 is provided at least over the semiconductor island 23b via an interlayer insulation film (not shown). The transparent electrode 25 is electrically connected to the drain electrode wiring 24b via a contact hole 26 which is provided in the interlayer insulation film. In a pixel section, the transparent electrode 25 is provided in a quadrangular pixel region surrounded by the gate electrodes wiring 21 and the source electrode wirings 24, and it is used as a pixel electrode.
Hereinafter, a conventional method for manufacturing the TFT substrate 20 will be described in detail with reference to Portion (a) of FIG. 9 to Portion (e) of FIG. 9.
Portion (a) of FIG. 9 to Portion (e) of FIG. 9 are top views showing an exemplary essential structure for describing each step of manufacturing the TFT substrate 20 in FIG. 8.
First, as shown in Portion (a) of FIG. 9, a step of forming the gate electrode wiring 21 and the compensation capacitance wiring 22 is performed. In this step, a glass substrate which becomes the TFT substrate 20 is cleaned by a WET cleaning or a DRY cleaning. Thereon, a metal material which becomes the gate electrode wiring 21 and the compensation capacitance (Cs) wiring 22 is deposited by a sputtering method or a CVD method. A resist mask is formed by a photolithography, and an etching is performed thereon by a WET etching or a DRY etching. As shown in Portion (a) of FIG. 9, the gate electrode wiring 21 and the compensation capacitance wiring 22 which are parallel to each other are formed, and the resist mask is removed by the WET method or the DRY method.
Next, as shown in Portion (b) of FIG. 9, a step of depositing the insulation film material and forming the semiconductor islands 23a and 23b is performed. In this step, the insulation film material which becomes the gate insulation film and the compensation capacitance insulation film, and the intrinsic semiconductor layer which becomes the channel region of the TFT and the part of the compensation capacitance upper electrode are deposited by the CVD method so as to form the impurity-doped semiconductor layer. A resist mask is formed by the photolithography, and an etching is performed thereon by the WET etching or the DRY etching. As shown in Portion (b) of FIG. 9, the semiconductor islands 23a and 23b are formed on the gate electrode wiring 21 and the compensation capacitance wiring 22 via the insulation films. The resist mask is removed by the WET method or the DRY method. In this case, in order to maintain the insulation between the source/drain electrode wirings which is to be formed later, and the gate electrode wiring, the insulation films with a thickness of about 500 nm deposited by the CVD method remains.
Further, as shown in Portion (c) of FIG. 9, a step of forming the source electrode wiring 24, the extension portion 24a and the drain electrode wiring 24b is performed. In this step, on the substrate where the insulation films and the semiconductor islands 23a and 23b are formed, a metal layer is deposited by the sputtering method or the CVD method. A resist mask is formed by the photolithography. An etching is performed thereon by the WET etching method or the DRY etching method so as to form, as shown in Portion (c) of FIG. 9, the extension portion 24a which is parallel to the gate electrode wiring 21 and the compensation capacitance wiring 22 and which extends onto the semiconductor island 23a, and the source electrode wiring 24 which is connected to the extension portion 24a, and the drain electrode wiring 24b which extends from the semiconductor island 23a to the semiconductor island 23b is formed. The resist mask is removed by the WET method or the DRY method.
Thereafter, as shown in Portion (d) of FIG. 9, a step of depositing the interlayer insulation film and forming the contact hole 26 is performed. In this step, the interlayer insulation film is deposited by the CVD method or the like on the substrate, as shown in Portion (c) of FIG. 9, where the source electrode wiring 24 and the extension portion 24a thereof and the drain electrode wiring 24b are formed, in order to electrically insulate between the source electrode wiring 24, the extension portion 24a thereof and the drain electrode wiring 24b, and the transparent electrode 25, which is to be formed later. In order to connect to the transparent electrode 25, which is to be formed later, a resist mask is formed on the interlayer insulation film by the photolithography method, an etching is performed thereon by the WET etching method or the DRY etching method, and as shown in Portion (d) of FIG. 9, the contact hole 26 is formed in the interlayer insulation film on the drain electrode wiring 24b overlying the semiconductor island 23b. The resist mask on the interlayer insulation film is removed by the WET method or the DRY method.
Lastly, as shown in Portion (e) of FIG. 9, a step of forming the transparent electrode is performed. In this step, a transparent electrode material is deposited on the interlayer insulation film and the contact hole 26 by the sputtering method or the CVD method. A resist mask is formed by the photolithography, and an etching is performed thereon by the WET etching method or the DRY etching method. As shown in Portion (e) of FIG. 9, the transparent electrode 25 is formed for each region surrounded by the gate electrode wirings 21 and the source electrode wirings 24. The resist mask is removed by the WET method or the DRY method.
The TFT substrate 20 manufactured in this manner is arranged opposite to a counter substrate having a counter electrode arranged thereon with a predetermined gap there between. The surrounding thereof is bonded. A liquid crystal material is implanted from an implantation opening into the gap between the substrates and the implantation opening is sealed. As such, a liquid crystal panel is formed.
As described above, in the conventional method for manufacturing the TFT, for example, in the case of the inversely staggered TFT, the fiver layers of masks are required in order to form the gate electrode wiring 21, the semiconductor islands 23a and 23b, the source/drain electrode wirings 24, 24a and 24b, the contact hole 26 and the transparent electrode 25. This is a cause of increasing the lead time, reducing the yield and increasing the manufacturing cost.
In addition, Reference 1 discloses, for example, a method for manufacturing a normally staggered TFT in which steps for the manufacturing are simplified and the TFT has excellent electric properties both in a drive circuit section and a pixel section. In the conventional technique disclosed in Reference 1, a resistance value is adjusted with an ion implantation, and six layers of masks of an LDD region mask, a drive circuit region LDD region mask, a channel region mask and the like are required.
[Reference 1] Japanese Laid-Open Publication No. 08-139335